CDx4ACT138 3-Line to 8-Line Decoders/Demultiplexers

1 Features

• Inputs are TTL-voltage compatible

• Speed of bipolar F, AS, and S, with significantly

reduced power consumption

• Designed specifically for high-speed memory

decoders and data-transmission systems

• Incorporate three enable inputs to simplify

cascading and/or data reception

• Balanced propagation delays

• ±24mA output drive current

– Fanout to 15 F devices

• SCR-latchup-resistant CMOS process and circuit

design

• Exceeds 2kV ESD protection per MIL-STD-883,

method 3015

2 Description

The ’ACT138 decoders/demultiplexers are designed

for high-performance memory-decoding and data-

routing

applications

that

require

very

short

propagation-delay

times.

In

high-performance

memory systems, these decoders can be used to

minimize the effects of system decoding.

Device Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

BODY SIZE(3)

CDx4ACT138

BQB (WQFN, 16)

3.5mm × 2.5mm

3.5mm × 2.5mm

D (SOIC, 16)

9.9mm × 6mm

9.9mm × 3.9mm

N (PDIP, 16)

19.3mm × 9.4mm

19.3mm × 6.35mm

PW (TSSOP, 16)

5.00mm × 6.4mm

5.00mm × 4.40mm

(1)

For more information, see Section 10.

(2)

The package size (length × width) is a nominal value and

includes pins, where applicable.

(3)

The body size (length × width) is a nominal value and does

not include pins.

Logic Diagram (Positive Logic)

CD54ACT138, CD74ACT138

SCHS329C – JANUARY 2003 – REVISED JULY 2024

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.