SAA7380GP datasheet(8/60 Pages) PHILIPS

8 / 60 page

1996 Apr 25

Philips Semiconductors

Preliminary speciﬁcation

Error correction and host interface IC for

CD-ROM (ELM)

SAA7380

6.1

Pin functions

6.1.1

RA0 TO RA14

External memory address signals.

6.1.2

RA16/CAS

External memory RA16 signal if SRAM or, CAS signal if

DRAM.

6.1.3

RA15/RAS

External memory RA15 signal if SRAM or, RAS signal if

DRAM.

6.1.4

RWE

Write output enable signal for external buffer memory. This

is LOW when the SAA7380 wants to write data into the

external memory.

6.1.5

RD0 TO RD7

External buffer memory bidirectional data signals.

6.1.6

SFSY

Frame sync for the Q-to-W subcode, indicates when

P-channel is available by a HIGH-to-LOW transition.

Frame 0 is also indicated by no transition on this line.

6.1.7

RCK

In response to SFSY going LOW data is clocked into the

SAA7380 before each rising edge using this clock output.

6.1.8

SUB

Q-to-W subcode is input in response to RCK in 3-wire EIAJ

mode or WS in “V4” mode compatible with the SAA7345.

6.1.9

BCK

Bit clock for the serial data input from the CD decoder.

6.1.10

Word clock for the serial data input from the CD decoder.

6.1.11

DATA

Serial data input from the CD decoder. This may be either

I2S-bus or EIAJ 16-bit format.

6.1.12

C2PO

Error flag from the CD decoder. A HIGH indicates that a

byte has not been corrected by the C2 error corrector and

therefore is not valid. This is taken into account by the

SAA7380 error corrector.

6.1.13

SDA

Sub-CPU bidirectional data signal. This signal forms part

of the 3-wire serial interface between the SAA7380 and the

sub-CPU.

6.1.14

SCL

Sub-CPU sync signal. This signal forms part of the 3-wire

serial interface between the SAA7380 and the sub-CPU.

This signal is used to synchronize data transfers between

the sub-CPU and the SAA7380.

6.1.15

INT

Sub-CPU interrupt signal. This active LOW output signals

to the sub-CPU that the SAA7380 has an interrupt request.

6.1.16

RESET

Forcing this input LOW resets the SAA7380.

6.1.17

SYN

Sub-CPU clock signal. This signal forms part of the 3-wire

serial interface between the SAA7380 and the sub-CPU.

This signal is the sub-CPU driven bit clock used to

synchronize the signals on the SDA line.

6.1.18

CS1/HEN

In the ATAPI mode this is the host chip select 1 address

signal. In the Sanyo and Oak compatibility modes setting

this input LOW enables the host interface.

6.1.19

HWR

This active LOW signal is the host write request.

6.1.20

HRD

This active LOW signal is the host read request.

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