7 Detailed Description

7.1 Overview

The SN74LVC166A is a parallel-load 8-bit shift register with asynchronous clear ( CLR). This parallel-in or

serial-in, serial-out shift register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input.

The parallel-in or serial-in modes are established by the mode select (SH/LD) input. When high, SH/LD enables

the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When

low, the parallel (A through H) data inputs are enabled, and synchronous loading occurs on the next clock pulse.

During parallel loading, serial data flow is inhibited. Clocking is accomplished on the rising edge of CLK or CLK

INH, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH

high inhibits clocking; holding either low enables the other clock input. CLK INH should be changed to the high

level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

7.2 Functional Block Diagram

D

Q

R

D

Q

R

SER

SH/LD

CLK INH

CLK

CLR

A

B

C

D

E

F

G

H

5 Additional

Shift Register

Stages

D

Q

R

QH

Figure 7-1. Logic Diagram (Positive Logic) for SN74LVC166A

7.3 Feature Description

7.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads, so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important to limit the output

power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute

Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs must be left disconnected.

SN74LVC166A

SCLSA15 – MAY 2024

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