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SAA7282ZP bảng dữ liệu(PDF) 7 Page - NXP Semiconductors |
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SAA7282ZP bảng dữ liệu(HTML) 7 Page - NXP Semiconductors |
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7 / 25 page ![]() July 1993 7 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 I2C-BUS FORMATS The SAA7282 contains an I2C-bus slave transceiver permitting a master device to: • Read decoder status information derived from the transmitted digital audio signal • Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal • Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future services to be implemented in receiver software • Write control codes to select the available analog switching configurations • Write upper and lower error count limits for automatic muting function The device slave address is A(7:1)(R/W) = 101101X(R/W). An ADSEL pin is provided to allow selection of one of two different slave addresses via programmable address bit A1. (X = ADSEL logic level). The SAA7282 does not acknowledge the I2C-bus general call address. The slave receiver format is: S SLAVE_ADDR.0 ACK SUB_ADDR ACK DATA BYTE ACK P <−n bytes−> Where S = start, ACK = acknowledge, P = stop. Auto-increment of the sub-address is provided with wrap-around from 02 (HEX) to 00 (HEX). The slave receiver data byte format, as a function of sub-address, is as shown in Table 1. Table 1 Slave receiver data byte. M1/M2 This bit in conjunction with DMSEL bit, determines the output configuration in dual mono mode (see Table 2). Power-on resets to logic 1. DMSEL This bit determines whether one or both of the dual mono signals are output (see Table 2). Power-on resets to logic 0. PORT2 PORT2 controls a bit out, providing direct access to a dedicated output pin (PORT2) via the I2C-bus. See Table 3. Power-on resets to logic 0. SSWIT3/2/1 These bits control the analog switching, selecting between the FM, external, and NICAM signals. With the NICAM source the signals select whether the de-emphasis is performed and what gain is applied after the filtering and de-emphasis stage. The signal states and their meaning are listed in Table 4. Power-on resets to 0/1/0. SUB- ADDRESS RESET VALUE HEX D7 D6 D5 D4 D3 D2 D1 D0 00 90 M1/M2 DMSEL SSWIT3 SSWIT2 SSWIT1 PORT2 MUTEDEF AMDIS 01 50 EMAX7 EMAX6 EMAX5 EMAX4 EMAX3 EMAX2 EMAX1 EMAX0 10 14 EMIN7 EMIN6 EMIN5 EMIN4 EMIN3 EMIN2 EMIN1 EMIN0 |
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