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2-579
RF5117C
Rev A5 060517
Evaluation Board Schematic - IEEE802.11g
2400MHz to 2483MHz
C1
10 pF
R2
390
Ω
R1
390
Ω
C15
1 nF
PWR SENSE
C16
1 nF
PS REF
C3
1 nF
VREG1
VREG2
C13
1 nF
L2
10 nH
L1
12 nH
C5
2.7 pF
JOH
C8
10 pF
C9
10 pF
C10
1 nF
C11
6.8 pF
JOH
C2
1 nF
Notes:
1. C7 - 130 mils from chip.
2. Pin 2 cut from ground.
3. C11 must be placed as close to chip as possible.
4. The VREG trace is cut and a 4.7 kΩ resistor is
placed on the trace.
Part is Backside Grounded.
C12
1 nF
J1
RF IN
50
Ω μstrip
VCC
50
Ω μstrip
J2
RF OUT
L3
1.2 nH
Murata
C17
2.7 pF
JOH
C14
1 nF
16
15
14
13
5
6
7
8
9
10
11
12
4
3
2
1
Bias
C23
1
μF
P1
1
2
3
4
5
CON5
GND
P1-4
VREG1
P1-5
VREG2
P1-1
PS REF
P1-2
PWR SENSE
GND
GND
P2-3
VCC
P2
1
2
3
CON3
P3-1
VCC
P3
1
CON1
P4
1
CON1
GND
R3
4.3 k
Ω
*1
*2
5117400B
*3
Place C11 as close
to chip as possible
C22
10
μF
TL1 = 130 mil (50
Ω)
*4
TL1
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