XRK39910 datasheet(4/9 Pages) EXAR

4 / 9 page

XRK39910

3.3V LOW SKEW PLL CLOCK DRIVER

REV. 1.0.0

NOTE: (1) These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected

inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL

may require an additional tLOCK time before all datasheet limits are achieved.

NOTE: (1) For eight outputs, each loaded with 20pF.

NOTE: (1) Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.

3-Level Input DC Current (BYPASS, FSEL)

VIN = VDD

HIGH Level

+400

μA

VIN = VDD/2

MID Level

+200

VIN = GND

LOW Level

+400

IPU

Input Pull-Up current (PE)

VDD = Max., VIN = GND

+100

μA

IPD

Input Pull-Down Current (OE)

VDD= Max., VIN = VDD

+100

μA

VOH

Output HIGH Voltage

VDD = Min., IOH = -12mA

2.4

VOL

Output LOW Voltage

VDD = Min., IOL = 12mA

0.55

TABLE 7: POWER SUPPLY CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS(1)

TYP.

MAX.

UNIT

IDDQ

Quiescent Power Supply Current

VDD=Max., BYPASS=MID, CLKIN=LOW

VDD/PE=LOW, OE=LOW,

All outputs unloaded

ITOT

Total Power Supply Current

VDD=3.3V, FREF=25MHz, CL=160pF(1)

VDD=3.3V, FREF=33MHz, CL=160pF(1)

VDD=3.3V, FREF=66MHz, CL=160pF(1)

TABLE 8: INPUT TIMING REQUIREMENTS

SYMBOL

DESCRIPTION(1)

MIN.

MAX.

UNIT

tR, tF

Maximum input rise and fall times, 0.8V to 2V

ns/V

tPWC

Input clock pulse, HIGH or LOW

Input duty cycle

Ref

Reference Clock Input

MHz

TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

SYMBOL

PARAMETER

CONDITIONS

MIN.MAX.UNIT

XRK39910 bảng dữ liệu(PDF) 4 Page - Exar Corporation

XRK39910 bảng dữ liệu(HTML) 4 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9

bảng dữ liệu tải về

Link URL