ST16C554/554D

13

REV. 4.0.1

2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO

2.10.1

Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 16 bytes by 11-bit wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

Receive Data Shift

Register (RSR)

Receive

Data Byte

and Errors

RHR Interrupt (ISR bit-2)

Receive Data

Holding Register

(RHR)

RXFIFO1

16X Clock

Receive Data Characters

Data Bit

Validation

Error

Tags in

LSR bits

4:2

Receive Data S hift

R egister (R S R )

RX FIFO 1

16X C lock

R eceive D ata C haracters

D ata B it

V alidation

Receive

D ata FIF O

Receive

Data

Receive Data

B yte and E rrors

R H R Interrupt (IS R bit-2) program m ed for

desired FIFO trigger level.

FIFO is E nabled by F C R bit-0=1

A sking for stopping data w hen data fills above the flow

control trigger level to suspend rem ote transm itter.

A sking for sending data w hen data falls below the flow

control trigger level to restart rem ote transm itter.

16 bytes by 11-bit w ide

FIFO

FIFO

T rigger=8

D ata falls to

4

D ata fills to

14

E xam ple

: - R X F IF O trigger level selected at 8 bytes

(See N ote Below )