công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

MPC8540CPX667JC bảng dữ liệu(PDF) 20 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8540CPX667JC
Giải thích chi tiết về linh kiện  Integrated Processor Hardware Specifications
PDF  104 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540CPX667JC bảng dữ liệu(HTML) 20 Page - Freescale Semiconductor, Inc

Back Button MPC8540CPX667JC Datasheet HTML 16Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 17Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 18Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 19Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 20Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 21Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 22Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 23Page - Freescale Semiconductor, Inc MPC8540CPX667JC Datasheet HTML 24Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 104 page
background image
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
20
Freescale Semiconductor
DDR SDRAM
Figure 5 shows the DDR SDRAM output timing diagram.
Figure 5. DDR SDRAM Output Timing Diagram
6.2.2.2
Load Effects on Address/Command Bus
Table 18 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings. These numbers are the result of simulations for one
topology. The delay numbers will strongly depend on the topology used. These delay numbers show the
total delay for the address and command to arrive at the DRAM devices. The actual delay could be
different than the delays seen in simulation, depending on the system topology. If a heavily loaded system
is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM.
Table 18. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
3.0
ns
9 devices (27 pF)
3.6
ns
36 devices (108 pF) + 40 pF compensation capacitor
5.0
ns
36 devices (108 pF) + 80 pF compensation capacitor
5.2
ns
ADDR/CMD
DLL Phase Alignment
tDDKHOV
tDDSHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MSYNC_IN
MSYNC_OUT
MCK[n]
MCK[n]
tMCK
tDDSHME
tDDKLDX
tDDKHDX
tDDSHMP
D1
D0
tDDKHOX
Write A0
NOOP
tMCK
tMCKH



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com