34652 datasheet(17/26 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34652

FUNCTIONAL DEVICE OPERATION

PROTECTION FEATURES

The power dissipation in the device can be calculated as

follows:

P = I2(LOAD) * RDS(ON)

P = [TJ(max) - TA(max)] / RθJA

Combining the two equations:

I2(LOAD) = [TJ(max) - TA(max)] / [RθJA * RDS(ON)] Eq 1

For example:

TA(max) = 55°C

RθJA = 51°C/W for a four-layer board

RDS(ON) = 0.251 Ω at high temperatures

Then:

I2(LOAD) = [TJ(max) - 55°C] / [51°C/W * 0.251 Ω]

I2(LOAD) = [TJ(max) - 55°C] / 12.80°C/A

So if the overcurrent limit is 2.0 A, then the maximum

junction temperature is 106.2°C, which is well below the

thermal shutdown temperature that is allowed.

The previous explanation applies to steady state power

when the device is in normal operation. During the charging

process, the power is dominated by the I* V across the Power

MOSFET. When charging starts, the power in the Power

MOSFET rises up and reaches a maximum value of I* V, then

quickly ramps back down to the steady state level in a period

governed by the size of the load’s input capacitor that is being

charged and by the value of the charging current limit ICHG.

In this case the instantaneous power dissipation is much

higher than the steady state case, but it is on for a very short

time.

For example:

ICHG = 100 mA, the default value

CLOAD = 400 µF, a very large capacitor

VPWR = 80 V, worst case

Then:

The power pulse magnitude = ICHG * VPWR = 8.0 W

The power pulse duration = CLOAD * VPWR/ICHG = 320 ms

Figure 17 displays the temperature profile of the device

under the instantaneous power pulse during the charging

process. Table 5 depicts thermal resistance values for

different board configurations.

Figure 17. Instantaneous Temperature Rise of an 8.0 W

0.0

10.0

20.0

30.0

40.0

50.0

60.0

100

200

300

400

Tim e (m illisec)

Time (ms)

Table 5. Thermal Resistance Data

Type

Condition

Symbol

Value

Unit

Junction to Ambient

Single-layer board (1s), per JEDEC JESD51-2 with board (JESD51-3) horizontal

RθJA

103

°C/W

Junction to Ambient

Four-layer board (2s2p), per JEDEC JESD51-2 with board (JESD51-3) horizontal

RθJMA

°C/W

Junction to Ambient

Single-layer board with a 300 mm2 radiator pad on its top surface, not standard JEDEC

—

°C/W

Junction to Ambient

Single-layer board with a 600 mm2 radiator pad on its top surface, not standard JEDEC

—

°C/W

Junction to Ambient

Four-layer board with a via for each thermal lead, not standard JEDEC

—

°C/W

Junction to Ambient

Four-layer board with a 300 mm2 radiator pad on its top surface and a full array of vias

between radiator pad and top surface, not standard JEDEC

—

°C/W

Junction to Ambient

Four-layer board with a 600 mm2 radiator pad on its top surface and a full array of vias

between radiator pad and top surface, not standard JEDEC

—

°C/W

Junction to Board

Thermal resistance between die and board per JEDEC JESD51-8

RθJB

°C/W

Junction to Case

Thermal resistance between die and case top

RθJC

°C/W

Junction to Package

Top

Temperature difference between package top and junction per JEDEC JESD51-2

°C/W

Junction to Lead

Thermal resistance between junction and thermal lead, not standard JEDEC

RθJL

°C/W

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