MC13201 Technical Data, Rev. 1.1,

12

Freescale Semiconductor

Figure 7. SPI Interface

Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock

registers and memory.

6.2.1

SPI Burst Operation

The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master

(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the

master on the MISO line. Although an MC13201 transaction is three or more SPI bursts long, the timing

of a single SPI burst is shown in Figure 8.

Figure 8. SPI Single Burst Timing Diagram

SPI digital timing specifications are shown in Table 6.

Shift Register

Baud Rate

Generator

Shift Register

Chip Enable (CE)

RxD

MISO

TxD

MOSI

Sclk

SPICLK

MCU

MC13201

CE

1

23

4

5

6

7

8

CE

SPICLK

T1

T2

T4

T0

SPI Burst

Valid

T5

T6

T3

Valid

T7

MISO

MOSI

Valid