NXP Semiconductors

A5M20TG042

Airfast Power Amplifier Module

A5M20TG042

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Product data sheet

Rev. 1 — 20 May 2024

9 / 21

Correct biasing sequence

Turn ON:

Bias ON the GaN final stage first (stage 3)

1. Set gate voltage VG3A and VG3B to –8 V.

2. Set drain voltage VD3A and VD3B to nominal supply voltage (+45 V).

3. Increase VG3B (peaking side) until IDQ3B = 50 mA current is attained, and then subtract 2.05 V for final VG3B bias

voltage.

4. Increase VG3A (carrier side) until IDQ3A current is attained.

Bias ON the LDMOS drivers second (stages 1 and 2)

5. Set drain voltage VD1 and VD2 to nominal supply voltage (+28 V), in no particular order.

6. Increase gate voltage VG2 until IDQ2 current is attained.

7. Increase gate voltage VG1 until IDQ1 current is attained.

8. Apply RF input power to desired level.

Turn OFF:

Bias OFF the GaN final stage first (stage 3)

1. Disable RF input power.

2. Adjust gate voltage VG3A and VG3B to –8 V.

3. Adjust drain voltage VD3A and VD3B to 0 V. Allow adequate time for drain voltage to reduce to 0 V from external

drain capacitors.

4. Disable VG3A and VG3B.

Bias OFF the LDMOS drivers second (stages 1 and 2)

5. Adjust gate voltage VG1 and VG2 to 0 V.

6. Adjust drain voltage VD1 and VD2 to 0 V.