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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADC3910CSSS bảng dữ liệu(PDF) 111 Page - Texas Instruments |
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ADC3910CSSS bảng dữ liệu(HTML) 111 Page - Texas Instruments |
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111 / 131 page  6.6.3.3 0x1B5 Register (Address = 1B5h) [Reset = 00h] Return to the Summary Table. Table 6-254. 0x1B5 Register Field Descriptions Bit Field Type Reset Description 7:0 ALERT_INVERT__15:8 R/W 0h Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. See register 0x1B4 for bit mask. 6.6.3.4 0x1B6 Register (Address = 1B6h) [Reset = 0h] Return to the Summary Table. Table 6-255. 0x1B6 Register Field Descriptions Bit Field Type Reset Description 2:0 ALERT_INVERT__18:16 R/W 0h Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. 6.6.3.5 0x1C0 Register (Address = 1C0h) [Reset = 00h] Return to the Summary Table. Table 6-256. 0x1C0 Register Field Descriptions Bit Field Type Reset Description 7:0 ALERT_TRIG__7:0 R/W 0h Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. 6.6.3.6 0x1C1 Register (Address = 1C1h) [Reset = 00h] Return to the Summary Table. Table 6-257. 0x1C1 Register Field Descriptions Bit Field Type Reset Description 7:0 ALERT_TRIG__15:8 R/W 0h Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. 6.6.3.7 0x1C2 Register (Address = 1C2h) [Reset = 0h] Return to the Summary Table. Table 6-258. 0x1C2 Register Field Descriptions Bit Field Type Reset Description 0 ALERT_TRIG__18:16 R/W 0h Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. 6.6.3.8 0x1CC Register (Address = 1CCh) [Reset = 00h] Return to the Summary Table. www.ti.com ADC3910D025, ADC3910D065, ADC3910D125 ADC3910S025, ADC3910S065, ADC3910S125 SBASAD1A – DECEMBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 |
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