ADC3910CSSS datasheet(49/131 Pages) TI1

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6.3.8.1 Bypass Test Pattern

The test pattern for low latency mode (digital bypassed) is enabled in SPI register TEST_PAT_CHx (0x91) and

configured in SPI register TEST_PATTERN_CHx (0x092).

6.3.8.2 Digital Test Pattern

The digital test pattern is enabled in SPI register DIG_PAT_EN (0x0A6) and configured in SPI registers

DIG_PATTERN_MODE_CHx (0x0A1) and DIG_PATTERN_CHx (0x0A2-0x0A5). The test pattern is 16 bits wide.

In 10 bit mode the MSB 10 bits are send out.

• RAMP Pattern: The step size can be configured as 1 (at 16 bit level) or the value assigned written in

DIG_PAT_CHx. To generate a ramp with step size of 1 in 10 bit mode the step size must be programmed to

64 in DIG_PAT_CHx.

• Custom Pattern: Configured in the DIG_PAT_CHx register

• Toggle Pattern: Either toggle between DIG_PAT_CHx and bitwise inversion of DIG_PAT_CHx or toggle

between DIG_PAT_CHx and 0.

6.4 Device Functional Modes

6.4.1 Normal Operation

In normal operating mode, the entire ADC full scale range gets converted to a digital output with 10-bit

resolution. The output is available in as little as 1 clock cycle on the digital outputs.

6.4.2 Power Down Options

A global or fast power down mode can be enabled via SPI as well as using the power down pin (OENZ/PDN).

There is an internal pull-down resistor on the OENZ/PDN input pin, and the pin is active HIGH. The pin needs to

be pulled high externally to enter power down mode. The SPI register map provides the capability to enable or

disable individual blocks directly or via PDN pin mask to trade off power consumption vs wake up time as shown

in the Timing Requirements table.

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ADC3910D025, ADC3910D065, ADC3910D125

ADC3910S025, ADC3910S065, ADC3910S125

SBASAD1A – DECEMBER 2023 – REVISED MAY 2024

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ADC3910CSSS bảng dữ liệu(PDF) 49 Page - Texas Instruments