Philips Semiconductors Programmable Logic Devices

Product specification

PLS100/PLS101

Programmable logic arrays

(16

× 48 × 8)

October 22, 1993

54

LOGIC PROGRAMMING

PLS100/PLS101 is fully supported by

industry standard (JEDEC compatible) PLD

CAD tools, including Philips Semiconductors’

SNAP, Data I/O Corporation’s ABEL

™ and

Logical Devices Inc.’s CUPL

™ design

software packages.

All packages allow Boolean and state

equation entry formats. SNAP, ABEL and

CUPL also accept, as input, schematic

capture format.

PLS100/PLS101 logic designs can also be

generated using the program table entry

format detailed on the following pages. This

program table entry format is supported by

the Philips Semiconductors’ SNAP PLD

design software package.

To implement the desired logic functions, the

state of each logic variable from logic

equations (I, B, O, P, etc.) is assigned a

symbol. The sumbols for TRUE,

COMPLEMENT, INACTIVE, PRESET, etc.,

are defined below.

PROGRAMMING AND

SOFTWARE SUPPORT

Refer to Section 9

(Development Software)

and Section 10

(Third-party Programmer/

Software Support) of this dat handbook for

additional informational.

OUTPUT POLARITY – (F)

CODE

ACTIVE LEVEL

LOW

(INVERTING)

H

S

X

O, B

CODE

ACTIVE LEVEL

HIGH1

(NON-INVERTING)

L

S

F

“AND” ARRAY – (I)

CODE

STATE

INACTIVE1,2

O

P

I

I

I

CODE

–

STATE

DON’T CARE

CODE

STATE

CODE

STATE

I

H

L

P

I

I

I

P

I

I

I

P

I

I

I

I

“OR” ARRAY – (F)

CODE

INACTIVE

A

CODE

Pn STATUS

ACTIVE1

•

P

S

P

S

Pn STATUS

NOTES:

1. This is the initial unprogrammed state of all links. It is normally associated with all unused

VIRGIN STATE

The PLS100/101 virgin devices are factory

shipped in an unprogrammed state, with all

fuses intact, such that:

AND array.

3. All outputs are Active-High.

ABEL is a trademark of Data I/O Corp.

CUPL is a trademark of Logical Devices, Inc.