PLHS501 datasheet(11/12 Pages) PHILIPS

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Philips Semiconductors Programmable Logic Devices

Product specification

PLHS501/PLHS501I

Programmable macro logic

PML

™

October 22, 1993

PLHS501 GATE AND SPEED ESTIMATE TABLE

FUNCTION

INTERNAL NAND

EQUVALENT

TYPICAL tPD

fMAX

COMMENTS

Gates

NANDs

6.5ns

For 1 to 32 input variables

ANDs

6.5ns

For 1 to 32 input variables

NORs

6.5ns

For 1 to 32 input variables

ORs

6.5ns

For 1 to 32 input variables

Decoders

3-to-8

11ns

Inverted inputs available

4-to-16

11ns

Inverted inputs available

5-to-32

11ns

Inverted inputs available (24 chip outputs only)

Encoders

8-to-3

11ns

Inverted inputs, 2 logic levels

16-to-4

11ns

Inverted inputs, 2 logic levels

32-to-5

11ns

Inverted inputs, 2 logic levels, factored solution.

Multiplexers

4-to-1

11ns

Inverted inputs available

8-to-1

11ns

16-to-1

11ns

27-to-1

11ns

Can address only 27 external inputs - more if internal

Flip-Flops

D-type Flip-Flop

30MHz

With asynchronous S-R

T-type Flip-Flop

30MHz

With asynchronous S-R

J-K-type Flip-Flop

30MHz

With asynchronous S-R

Adders

8-bit

15.5ns

Full carry-lookahead (four levels of logic)

Barrel Shifters

8-bit

11ns

2 levels of logic

Latches

D-latch

2 levels of logic with one shared gate

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