AD9991KCPRL datasheet(12/60 Pages) AD

tên linh kiện	AD9991KCPRL

Giải thích chi tiết về linh kiện	10-Bit CCD Signal Processor with Precision Timing ??Generator

PDF	60 Pages

Scroll/Zoom	100%

nhà sản xuất	AD [Analog Devices]

Trang chủ	http://www.analog.com

Logo

12 / 60 page

AD9991

–12–

P[0]

PIXEL

PERIOD

H1/H3

RGf[12]

P[48] = P[0]

Hf[24]

CCD

SIGNAL

P[24]

P[12]

P[36]

Hr[0]

RGr[0]

SHD[0]

NOTES

ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

POSITION

tS1

H2/H4

SHP[24]

Figure 7. High Speed Timing Default Locations

NOTES

DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

OUTPUT DELAY (

OD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

P[0]

P[48] = P[0]

PIXEL

PERIOD

P[12]

P[24]

P[36]

DOUT

DCLK

Figure 8a. Digital Output Phase Adjustment

NOTES

DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0.

HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

DCLK

DOUT

CCDIN

CLI

SHD

(INTERNAL)

N+1

N+2

N+12

N+11

N+10

N+9

N+8

N+7

N+6

N+5

N+4

N+3

N+13

N-13

N-3

N-4

N-5

N-6

N-7

N-8

N-9

N-10

N-11

N-12

N-2

N-1

N+1

SAMPLE PIXEL N

PIPELINE LATENCY=11 CYCLES

CLIDLY

N-1

N+2

Figure 8b. Pipeline Delay

REV. 0

AD9991KCPRL bảng dữ liệu(PDF) 12 Page - Analog Devices

AD9991KCPRL bảng dữ liệu(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

bảng dữ liệu tải về

Link URL