DSP56852 datasheet(33/48 Pages) FREESCALE

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Synchronous Serial Interface (SSI) Timing

56852 Technical Data, Rev. 8

Freescale Semiconductor

4.10 Synchronous Serial Interface (SSI) Timing

Table 4-11 SSI Master Mode1 Switching Characteristics

Operating Conditions: VSS = VSSIO = VSSA = 0V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, fop = 120MHz

1. Master mode is internally generated clocks and frame syncs

Parameter

Symbol

Min

Typ

Max

Units

STCK frequency

152

MHz

STCK period3

tSCKW

66.7

STCK high time

tSCKH

33.4

STCK low time

tSCKL

33.4

Output clock rise/fall time

Delay from STCK high to STFS (bl) high - Master4

tTFSBHM

-1.0

-0.1

Delay from STCK high to STFS (wl) high - Master4

tTFSWHM

-1.0

-0.1

Delay from SRCK high to SRFS (bl) high - Master4

tRFSBHM

0.1

1.0

Delay from SRCK high to SRFS (wl) high - Master4

tRFSWHM

0.1

1.0

Delay from STCK high to STFS (bl) low - Master4

tTFSBLM

-1.0

-0.1

Delay from STCK high to STFS (wl) low - Master4

tTFSWLM

-1.0

-0.1

Delay from SRCK high to SRFS (bl) low - Master4

tRFSBLM

-0.1

0.1

Delay from SRCK high to SRFS (wl) low - Master4

tRFSWLM

-0.1

0.1

STCK high to STXD enable from high impedance - Master

tTXEM

STCK high to STXD valid - Master

tTXVM

STCK high to STXD not valid - Master

tTXNVM

-0.1

STCK high to STXD high impedance - Master

tTXHIM

-4

SRXD Setup time before SRCK low - Master

tSM

SRXD Hold time after SRCK low - Master

tHM

Synchronous Operation (in addition to standard internal clock parameters)

SRXD Setup time before STCK low - Master

tTSM

SRXD Hold time after STCK low - Master

tTHM

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