DSP56366 datasheet(62/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

3-36

Freescale Semiconductor

Figure 3-18 Asynchronous Bus Arbitration Timing

Figure 3-19 Asynchronous Bus Arbitration Timing

Background explanation for Asynchronous Bus Arbitration:

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is negated.

This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted

before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to

assume mastership at the same time. Therefore some non-overlap period between one BG input active to

another BG input active is required. Timing 251 ensures that such a situation is avoided.

BG1

250

251

BG2

BG1

BG2

250+251

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