PHN708 datasheet(3/12 Pages) PHILIPS

3 / 12 page

1998 Mar 17

Philips Semiconductors

Product speciﬁcation

7 N-channel 80 m

Ω FET array

enhancement mode MOS transistors

PHN708

QUICK REFERENCE DATA

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Ts is the temperature at the soldering point of the drain lead.

2. Pulse width and duty cycle limited by maximum junction temperature.

3. When only one FET dissipates.

4. When either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power.

5. When FET four plus either combination of FETs 1-5, 1-6, 2-5, 2-7, 3-6 or 3-7 dissipate an equal amount of power.

6. When all seven FETs dissipate an equal amount of power.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

VDS

drain-source voltage (DC)

−

VGS

gate-source voltage (DC)

−±20

VGSth

gate-source threshold voltage

ID = 1 mA; VDS =VGS

2.8

drain current (DC)

Ts =80 °C

−

3.1

RDSon

drain-source on-state resistance

ID = 1.5 A; VGS =10V

−

Ω

Ptot

total power dissipation

Ts =80 °C

−

1.3

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Per FET

VDS

drain-source voltage (DC)

−

VGS

gate-source voltage (DC)

−±20

drain current (DC)

Ts =80 °C; note 1

−

3.1

IDM

peak drain current

note 2

−

12.4

Ptot

total power dissipation

Ts =80 °C; note 3

−

1.3

Ts =80 °C; note 4

−

1.13

Ts =80 °C; note 5

−

0.92

Ts =80 °C; note 6

−

0.77

Tstg

storage temperature

−55

+150

°C

operating junction temperature

−55

+150

°C

Source-drain diode

source current (DC)

Ts =80 °C

−

1.3

ISM

peak source current

note 2

−

5.2

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