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TFP401, TFP401A
TI PanelBus DIGITAL RECEIVER
SLDS120B - MARCH 2000 − REVISED JUNE 2003
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
PD
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-3),
HSYNC, VSYNC, SCDT
tpd(PDL)
PDO
QE(0-23), QO(0-23),
ODCK, DE, CTL(2-3),
HSYNC, VSYNC
tpd(PDOL)
VIL
VIL
Figure 7. Delay From PD Low to Hi-Z Outputs
Figure 8. Delay From PDO Low to Hi-Z Outputs
PD
DFO, ST, PIXS, STAG,
Rx(0-2)+, Rx(0-2)-,
OCK_INV
VIH
tp(PDH-V)
twL(PDL_MIN)
PD
Figure 9. Delay From PD Low to High Before
Inputs are Active
Figure 10. Minimum Time PD Low
VIL
tccs
50%
50%
TX2
TX1
TX0
Figure 11. Analog Input Channel-to-Channel Skew
tt(HSC)
tt(FSC)
DE
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
tDEL
tDEH
DE
Figure 13. Minimum DE Low and Maximum DE High
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