ADATE207 datasheet(4/36 Pages) AD

4 / 36 page

ADATE207

Rev. 0 | Page 4 of 36

AC SPECIFICATIONS

TC = 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ

Max

Unit

CLOCK INPUTS

Master Clock (MCLK) Frequency

100

MHz

MCLK Duty Cycle

DRIVE OUTPUTS

Output Pulse Width

Timing error < ±125 ps

COMPARE INPUTS

Minimum Comparison Window Width

1.25

Minimum Detectable Glitch Width

1.25

EDGE PERFORMANCE

Retrigger Time

2.5

Edge Delay

Lesser of 4 T0 cycles

or 163.8 μs

Vernier Resolution

39.06

Vernier Timing DNL

−150

+150

Vernier Timing INL

−150

+150

Vernier Temperature Coefficient

ps/°C

Edge Jitter

MCLK jitter 5 ps rms

ps rms

CONTROL AND STATUS REGISTER (CSR) INTERFACE

Clock Period

Setup Time (tBSU)

MCLK

1.1

Hold Time (tBH)

MCLK

0.5

Clock to Output (tBCO)

MCLK

2.5

7.0

Clock to Tristate (tBCZ)

2.3

4.2

Clock to Data Valid from Tristate (tBCZV)

7.0

DIGITAL INPUTS

Set Up (tISU)

MCLK

1.7

Hold Time (tIH)

MCLK

0.5

DIGITAL OUTPUTS

Clock to Output (tOCO)

MCLK

0.7

1.6

JTAG PORTS

JTAG Clock Period

100

Setup Time (tSSU)

JTAG CLOCK

Hold Time (tSH)

JTAG CLOCK

Clock to Output (tSCO)

JTAG CLOCK

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