AD9516-1SLASHPCBZ datasheet(5/84 Pages) AD

5 / 84 page

AD9516-1

Rev. 0 | Page 5 of 84

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

100

MHz

Antibacklash pulse width = 1.3 ns, 2.9 ns

MHz

Antibacklash pulse width = 6.0 ns

Antibacklash Pulse Width

1.3

0x17<1:0> = 01b

2.9

0x17<1:0> = 00b; 0x17<1:0> = 11b

6.0

0x17<1:0> = 10b

CHARGE PUMP (CP)

ICP Sink/Source

Programmable

High Value

4.8

With CPRSET = 5.1 kΩ

Low Value

0.60

Absolute Accuracy

2.5

CPV = VCP/2

CPRSET Range

2.7/10

kΩ

ICP High Impedance Mode Leakage

Sink-and-Source Current Matching

0.5 < CPV < VCP − 0.5 V

ICP vs. CPV

1.5

0.5 < CPV < VCP − 0.5 V

ICP vs. Temperature

CPV = VCP/2 V

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD

300

MHz

P = 2 FD

600

MHz

P = 3 FD

900

MHz

P = 2 DM (2/3)

600

MHz

P = 4 DM (4/5)

1000

MHz

P = 8 DM (8/9)

2400

MHz

P = 16 DM (16/17)

3000

MHz

P = 32 DM (32/33)

3000

MHz

Prescaler Output Frequency

300

MHz

A, B counter input frequency (prescaler

input frequency divided by P)

PLL DIVIDER DELAYS

000

Off

001

330

010

440

011

550

100

660

101

770

110

880

111

990

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Means Within the LBW

of the PLL)

The PLL in-band phase noise floor is estimated

by measuring the in-band phase noise at the

output of the VCO and subtracting 20log(N)

(where N is the value of the N divider)

@ 500 kHz PFD Frequency

−165

dBc/Hz

@ 1 MHz PFD Frequency

−162

dBc/Hz

@ 10 MHz PFD Frequency

−151

dBc/Hz

@ 50 MHz PFD Frequency

−143

dBc/Hz

PLL Figure of Merit (FOM)

−220

dBc/Hz

Reference slew rate > 0.25 V/ns. FOM +10log (fPFD)

is an approximation of the PFD/CP in-band

phase noise (in the flat region) inside the PLL

loop bandwidth. When running closed loop,

the phase noise, as observed at the VCO output,

is increased by 20log(N)

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