TMS320F28P550SD datasheet(39/268 Pages) TI1

39 / 268 page

Table 5-1. Pin Attributes (continued)

SIGNAL NAME

MUX POSITION

128

PDT

100

80 PNA

56 RSH

TYPE

DESCRIPTION

GPIO242

0, 4, 8, 12

I/O

General-Purpose Input Output 242 This pin also has

analog functions which are described in the ANALOG

section of this table.

EPWM11_A

ePWM-11 Output A

OUTPUTXBAR2

Output X-BAR Output 2

SPIA_PTE

I/O

SPI-A Peripheral Transmit Enable (PTE)

EPWM4_A

ePWM-4 Output A

MCANA_RX

CAN/CAN FD Receive

EQEP1_INDEX

I/O

eQEP-1 Index

ADCE_EXTMUXSEL2

ADCE external mux selection pin for position 2

GPIO247

0, 4, 8, 12

I/O

General-Purpose Input Output 247 This pin also has

analog functions which are described in the ANALOG

section of this table.

EPWM12_B

ePWM-12 Output B

GPIO253

0, 4, 8, 12

I/O

General-Purpose Input Output 253

EPWM12_A

ePWM-12 Output A

TEST, JTAG, AND RESET

TCK

JTAG test clock with internal pullup.

TMS

I/O

JTAG test-mode select (TMS) with internal pullup. This

serial control input is clocked into the TAP controller on

the rising edge of TCK. This device does not have a

TRSTn pin. An external pullup resistor (recommended

2.2 kΩ) on the TMS pin to VDDIO should be placed

on the board to keep JTAG in reset during normal

operation.

XRSn

I/OD

Device Reset (in) and Watchdog Reset (out). During

a power-on condition, this pin is driven low by the

device. An external circuit may also drive this pin to

assert a device reset. This pin is also driven low by the

MCU when a watchdog reset occurs. During watchdog

reset, the XRSn pin is driven low for the watchdog

reset duration of 512 OSCCLK cycles. A resistor

between 2.2 kΩ and 10 kΩ should be placed between

XRSn and VDDIO. If a capacitor is placed between

XRSn and VSS for noise filtering, it should be 100

nF or smaller. These values will allow the watchdog

to properly drive the XRSn pin to VOL within 512

OSCCLK cycles when the watchdog reset is asserted.

This pin is an open-drain output with an internal pullup.

If this pin is driven by an external device, it should be

done using an open-drain device.

POWER AND GROUND

VDD

6, 54,

90, 108

4, 71,

8, 53,

4, 44,

5, 41,

1.2-V Digital Logic Power Pins. TI recommends

placing a decoupling capacitor near each VDD pin with

a minimum total capacitance of approximately 10 µF.

It is also recommended that all VDD pins be externally

connected to each other when internal VREG is used.

VDDA

3.3-V Analog Power Pins. Place a minimum 2.2-µF

decoupling capacitor on each pin.

VDDIO

5, 55,

89, 109

3, 70,

7, 52,

43, 60 40, 54

3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF

decoupling capacitor on each pin.

VREGENZ

Internal voltage regulator enable with internal

pulldown. Tie low to VSS to enable internal VREG. Tie

high to VDDIO to use an external supply.

VSS

7, 53,

92, 107

5, 45,

72, 86

9, 30,

55, 70

5, 26,

45, 58

PAD

Digital Ground

VSSA

Analog Ground

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TMS320F28P550SJ, TMS320F28P559SJ-Q1

SPRSP85 – APRIL 2024

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