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MMA6281QR2 bảng dữ liệu(PDF) 5 Page - Freescale Semiconductor, Inc |
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MMA6281QR2 bảng dữ liệu(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 12 page ![]() Sensors Freescale Semiconductor 5 MMA6281QT BASIC CONNECTIONS Pin Descriptions Figure 4. Pinout Description Figure 5. Accelerometer with Recommended Connection Diagram PCB Layout Figure 6. Recommended PCB Layout for Interfacing Accelerometer to Microcontroller NOTES: 1. Use 0.1 µF capacitor on VDD to decouple the power source. Do not exceed capacitor values of 2.2 or 3.3 µF. Slow dV/dt rise times on VDD may cause the device to not power up below 0°C.To ensure operation below 0°C ensure VDD line has the ability to reach 2.2V in < 0.1 ms as measured on the device at the VDD pin. If output signal does not assert itself, then the dv/dt at the VDD pin of the device should be measured. 2. Physical coupling distance of the accelerometer to the microcontroller should be minimal. 3. The flag underneath the package is internally connected to ground. It is not recommended for the flag to be soldered down. 4. Place a ground plane beneath the accelerometer to reduce noise, the ground plane should be attached to all of the open ended terminals shown in Figure 6. 5. Use an RC filter with 1.0 kΩ and 0.1 µF on the outputs of the accelerometer to minimize clock noise (from the switched capacitor filter circuit). 6. PCB layout of power and ground should not couple power supply noise. 7. Accelerometer and microcontroller should not be a high current path. 8. A/D sampling rate and any external power supply switching frequency should be selected such that they do not interfere with the internal accelerometer sampling frequency (11 kHz for the sampling frequency). This will prevent aliasing errors. 9. PCB layout should not run traces or vias under the QFN part. This could lead to ground shorting to the accelerometer flag. Table 4. Pin Descriptions Pin No. Pin Name Description 1 g-Select1 Logic input pin to select g level. 2 g-Select2 Logic input pin to select g level. 3VDD Power Supply Input 4VSS Power Supply Ground 5 - 7 N/C No internal connection. Leave unconnected. 8 - 11 N/C Unused for factory trim. Leave unconnected. 12 Sleep Mode Logic input pin to enable product or Sleep Mode. 13 ZOUT Z direction output voltage. 14 N/C No internal connection. Leave unconnected. 15 XOUT X direction output voltage. 16 N/C No internal connection. Leave unconnected. Top View 15 16 14 13 12 11 10 1 2 3 4 56 7 8 9 g-Select1 N/C N/C N/C g-Select2 VDD VSS Sleep Mode Sleep Mode VDD VSS 3 4 VDD 0.1 µF 0.1 µF 15 12 XOUT 1 kΩ Logic Input 2 1 0.1 µF 13 ZOUT 1 kΩ Logic Inputs g-Select2 g-Select1 MMA6281QT POWER SUPPLY VDD VSS Sleep Mode g-Select1 g-Select2 XOUT ZOUT VDD VSS VRH P0 P1 P2 A/DIN A/DIN C C C R R C C C C |
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