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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 27

uses a monotonous linear conversion, or piece wise linear conversion when in companding mode.

Prior to A/D conversion, the signal value is stored on a Sample-and-Hold block after CDS block. The

result of conversion is stored in SRAM to be processed in digital domain.

7.3.1

ADC Linear Mode

Figure 34:

ADC Transfer Function in Linear Mode

7.3.2

ADC Companding Mode

The "companding" ADC mode allows to adapt the A/D conversion step to the increasing amount of

photon shot noise, which is inherent to the impinging optical signal as signal levels increase. This can

selectively amplify low light level signals. To ease re-linearization for further image treatment, the A/D

conversion step is doubled after each threshold. There are maximum three programmable thresholds

available. The thresholds are programmed over the serial configuration interface with a resolution of 8

bits, mapped to the 8 MSB of the conversion range. If using companding ADC mode, the three

thresholds must be strictly monotonous and smaller than the end of range register content.

Figure 35:

ADC Transfer Function in Companding Mode

ADC End Range

(Register 0x0A)

ADC Step (Register

0x04 to Line 1)

ADC Black Level

(Register 0x06)

ADC End Range

ADC Step

ADC Black Level

ADC Threshold 3

ADC Threshold 2

ADC Threshold 1

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