33889 datasheet(48/60 Pages) FREESCALE

tên linh kiện	33889

Giải thích chi tiết về linh kiện	System Basis Chip with Low Speed Fault Tolerant CAN Interface

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33889

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Table 24. Status bits

TIM REGISTERS

Description: This register is split into 2 sub registers, TIM1 and TIM2.

TIM1 controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0.

TIM2 is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is 1.

No read operation is allowed for registers TIM1 and TIM2

TIM REGISTER

Table 25. TIM Register.

L0WUb

L0WUa

FDIS bit in CAN

Description

No wake-up occurred at L0 (sleep or stop mode).

Low level state on L0 (standby or normal mode)

Wake-up occurred at L0 (sleep or stop mode).

High level state on L0 (standby or normal mode)

Wake-up occurred at L0 (sleep or stop mode with L0 filter disable). WUR must be set

to xx00 before sleep or stop mode.

L1WUb

L1WUa

Description

No wake-up occurred at L1 (sleep or stop mode).

Low level state on L1 (standby or normal mode)

Wake-up occurred at L1 (sleep or stop mode).

High level state on L1 (standby or normal mode)

TIM1

$101b

WDW

WDT1

WDT0

Reset

Reset condition

POR, RESET

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