56F8323 datasheet(82/140 Pages) FREESCALE

82 / 140 page

56F8323 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

5.6.30.4

Interrupt Disable (INT_DIS)—Bit 5

This bit allows all interrupts to be disabled.

•

0 = Normal operation (default)

•

1 = All interrupts disabled

5.6.30.5

Reserved—Bit 4

This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.

5.6.30.6

Reserved—Bit 3

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.30.7

IRQA State Pin (IRQA STATE)—Bit 2

This read-only bit reflects the state of the external IRQA pin.

5.6.30.8

Reserved—Bit 1

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.30.9

IRQA Edge Pin (IRQA Edg)—Bit 0

This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait

modes, it is automatically level-sensitive.

•0 = IRQA interrupt is a low-level sensitive (default)

•1 = IRQA interrupt is falling-edge sensitive

5.7 Resets

5.7.1

Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset

vector will be presented until the second rising clock edge after RESET is released.

5.7.2

ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except

the core IRQs with fixed priorities

•

Illegal Instruction

•

SW Interrupt 3

•

HW Stack Overflow

•

Misaligned Long Word Access

•

SW Interrupt 2

•

SW Interrupt 1

•

SW Interrupt 0

•

SW Interrupt LP

These interrupts are enabled at their fixed priority levels.

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