TSL2584TSVM datasheet(23/34 Pages) OSRAM

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[v1-08] 2017-Aug-28

TSL2584TSV − Register Description

Manual Integration Timer Registers (18h-19h)

The Manual Integration Timer Registers provide the number of

cycles in 10.9 μs increments that occurred during a manual

start/stop integration period. The timer is expressed as a 16-bit

value across two registers. See CONTROL and TIMING Registers

for further instructions in configuring a manual integration. The

maximum time that can be derived without an overflow is

714.3ms.

Figure 26:

Manual Integration Timer Registers

ID2 Register (1Eh)

The ID2 Register provides the means to identify the device as

TSL2584TSV. Although this is a W/R register, it is strongly

advised that this register not be written to. Any value written

to this register could adversely affect the performance of the

device.

Figure 27:

ID2 Register

TIMER

Address

Bits

Description (Reset = 00h)

TIMERLOW

18h

7:0

Manual Integration Timer lower byte

TIMERHIGH

19h

7:0

Manual Integration Timer upper byte

ID2

Reserved

Field

Bits

Description

ID2

This bit will be set (1) for all TSL2584TSV devices

Reserved

6:0

Reserved

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