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TSL2561 bảng dữ liệu(PDF) 16 Page - OSRAM GmbH

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Page 15
[v1-01] 2018-Apr-23
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TSL2561 − Principles of Operation
Command Register
The Command Register specifies the address of the target
register for subsequent read and write operations. The Send
Byte protocol is used to configure the Command Register. The
Command Register contains eight bits as described in
Figure 15. The Command Register defaults to 00h at power on.
Figure 15:
Command Register
Note(s):
1. An I²C block transaction will continue until the Master sends a stop condition.
7
6
5432
10
CMD
CLEAR
WORD
BLOCK
ADDRESS
Field
Bit
Description
CMD
7
Select Command Register. Must write as 1.
CLEAR
6
Interrupt clear. Clears any pending interrupt. This bit is a write-one-to-clear bit. It is
self clearing.
WORD
5
I2C Write/Read Word Protocol. 1 indicates that this I2C transaction is using either
the I2C Write Word or Read Word protocol.
BLOCK
4
Block Write/Read Protocol. 1 indicates that this transaction is using either the Block
Write or the Block Read protocol.(1)
ADDRESS
3:0
Register Address. This field selects the specific control or status register for
following write and read commands according to Figure 14.



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