TCS37209 datasheet(34/88 Pages) OSRAM

34 / 88 page

Datasheet, Public

Page 33

[v5-00] 2023-Nov-27

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TCS3720 − Register Overview

The frequency of consecutive ALS clear channel results outside

of threshold limits are counted; this count value is compared

against the APERS value. If the counter is equal to the APERS

setting an interrupt is asserted. Any time an ALS clear channel

result is inside the threshold values the counter is cleared.

CFG0 Register (Address 0x8D)

Figure 39:

CFG0 Register

PCFG0 Register (Address 0x8E)

Figure 40:

PCFG0 Register

Addr: 0x8D

CFG0

Bit

Bit Name

Default

Access

Bit Description

ENAB_16_

BIT_OP

0RW

Enables output of PDATA to be a 16-bit value when

APC is on. See PDATA (0xF4 and 0xF5) for details.

6:4

Reserved

001

Reserved. Must be set to default value.

3PWLONG

When PWLONG (PROX Wait Long) is asserted the wait

period as set by PWTIME is increased by a factor of 12.

2AWLONG

When AWLONG (ALS Wait Long) is asserted the wait

period as set by AWTIME is increased by a factor of 12.

1:0

Reserved

Reserved. Must be set to default value.

Addr: 0x8E

PCFG0

Bit

Bit Name

Default

Access

Bit Description

7:5

PGAIN

010

This field sets proximity first stage gain control.

Value

Stage 1 Gain

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

16x

4:2

Reserved

000

Reserved. Must be set to default value.

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