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ISO1228DFBR bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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ISO1228DFBR bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 44 page ![]() Table 4-1. Pin Functions—38 Pins (continued) PIN I/O DESCRIPTION NO. NAME 16 AVCC — Field Side Power Supply 17 AVSS — Field Side Negative Supply 18 IN8 I/O Field Input, Channel 8 19 LED8 I/O LED Indication Pin, Channel 8 20 NC — Leave unconnected 21 GND1 — Logic Ground 22 NC — Leave unconnected 23 F1 I Digital Filter Setting 24 F0 I Digital Filter Setting 25 GND1 — Logic Ground 26 nFAULT O Open Drain Ouput. Connect 4.7 kΩ pull-up to VCC1 27 OUT_EN I Ouput Enable. Output pins OUT1 through OUT8 are tri-stated if OUT_EN=0 or FLOAT 28 OUT8/SYNC O Synchronize data in Burst Mode(COMM_SEL=VCC1) Data Output, Channel 8, in Parallel Interface Mode (COMM_SEL=0) 29 OUT7/ BURST_EN I/O Burst Mode in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 7, in Parallel Interface Mode (COMM_SEL=0) 30 OUT6/nRST I/O Active Low SPI Reset in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 6, in Parallel Interface Mode (COMM_SEL=0) 31 OUT5/nINT O Active Low SPI Interrupt in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 5, in Parallel Interface Mode (COMM_SEL=0) 32 OUT4/nCS I/O SPI Chip Seltect in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 4, in Parallel Interface Mode (COMM_SEL=0) 33 OUT3/SCLK I/O SPI Clock in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 3, in Parallel Interface Mode (COMM_SEL=0) 34 OUT2/SDI I/O SPI Input Data in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 2, in Parallel Interface Mode (COMM_SEL=0) 35 OUT1/SDO O SPI Output Data in Serial Interface Mode (COMM_SEL=VCC1) Data Output, Channel 1, in Parallel Interface Mode (COMM_SEL=0) 36 GND1 — Logic Ground 37 VCC1 — Logic Supply 38 COMM_SEL I Serial vs. Parallel Interface selection Serial Interface Mode if COMM_SEL=VCC1 Parallel Interface Mode if COMM_SEL=0 or Floating • I = Input, O = Output, I/O = Input/Output • Connect all AVSS pins on Field side together • Connect all GND1 pins on backplane/MCU side together ISO1228 SLLSFN5A – JUNE 2023 – REVISED FEBRUARY 2024 www.ti.com 4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ISO1228 |
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