DP83816 datasheet(39/106 Pages) NSC

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4.0 Register Set (Continued)

4.2.1 Command Register

This register is used for issuing commands to DP83816. These commands are issued by setting the corresponding bits

for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are

provided here.

Tag: CR

Size: 32 bits

Hard Reset: 00000000h

Offset: 0000h

Access: Read Write

Soft Reset: 00000000h

Bit

Bit Name

Description

31-9

unused

RST

Reset

Set to 1 to force the DP83816 to a soft reset state which disables the transmitter and receiver,

reinitializes the FIFOs, and resets all affected registers to their soft reset state. This operation implies

both a TXR and a RXR. This bit will read back a 1 during the reset operation, and be cleared to 0 by the

hardware when the reset operation is complete. EEPROM configuration information is not loaded here.

SWI

Software Interrupt

Setting this bit to a 1 forces the DP83816 to generate a hardware interrupt. This interrupt is mask-able

via the IMR.

unused

RXR

Receiver Reset

When set to a 1, this bit causes the current packet reception to be aborted, the receive data and status

FIFOs to be flushed, and the receive state machine to enter the idle state (RXE goes to 0). This is a

write-only bit and is always read back as 0.

TXR

Transmit Reset

When set to a 1, this bit causes the current transmission to be aborted, the transmit data and status

FIFOs to be flushed, and the transmit state machine to enter the idle state (TXE goes to 0). This is a

write-only bit and is always read back as 0.

RXD

Receiver Disable

Disable the receive state machine after any current packets in progress. When this operation has been

completed the RXE bit will be cleared to 0. This is a write-only bit and is always read back as 0. The

driver should not set both RXD and RXE in the same write, the RXE will be ignored, and RXD will have

precedence.

RXE

Receiver Enable

When set to a 1, and the receive state machine is idle, then the receive machine becomes active. This bit

will read back as a 1 whenever the receive state machine is active. After initial power-up, software must

insure that the receiver has completely reset before setting this bit (See ISR:RXRCMP).

TXD

Transmit Disable

When set to a 1, halts the transmitter after the completion of the current packet. This is a write-only bit

and is always read back as 0. The driver should not set both TXD and TXE in the same write, the TXE

will be ignored, and TXD will have precedence.

TXE

Transmit Enable

When set to a 1, and the transmit state machine is idle, then the transmit state machine becomes active.

This bit will read back as a 1 whenever the transmit state machine is active. After initial power-up,

software must insure that the transmitter has completely reset before setting this bit (See ISR:TXRCMP).

DP83816 bảng dữ liệu(PDF) 39 Page - National Semiconductor (TI)

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