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SCL

SDA

DataLine

Stable;

DataValid

ChangeofData Allowed

Start

Condition

ClockPulsefor

Acknowledgement

Acknowledge

Not Acknowledge

DataOutput

byReceiver

DataOutput

byTransmitter

SCL From

Master

S

1

2

8

9

SCL

SDA

MSB

Slave Address

Data

Stop

1

2

3

4

5

6

7

8

9

9

1

2

3

4

5

6

7

8

9

Acknowledge

Acknowledge

THS7347

SLOS531 – MAY 2007

APPLICATIONS INFORMATION (continued)

• The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from

the slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. So, an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long

as necessary (see Figure 8).

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low

to high while the SCL line is high (see Figure 5). This transaction releases the bus and stops the

Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start

condition followed by a matching address.

17

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