ACT86600 datasheet(21/56 Pages) QORVO

21 / 56 page

ACT86600

Hybrid PMIC for Enterprise

Storage and Computing

Data Sheet Rev. B, February 2, 2023

Subject to change without notice

21 of 56

www.qorvo.com

Freq = 1110, VIN = 12.0V, VFB1 = 3.3V

1.8

MHz

Freq = 1111, VIN = 12.0V, VFB1 = 3.3V

1.9

MHz

Emulated switching frequency

accuracy

At the default switching frequency setting

-20

Soft-Start Period TSS

5% to 95% VNOM

1000

1500

µs

Tstart, Time from EN to PG

Time from enable to PGOOD

1200

µs

Peak Current Limit (per phase),

Cycle-by-Cycle

ILIM set = 00, per single phase

ILIM set = 01, per single phase

ILIM set = 10, per single phase (Note 2)

ILIM set = 11, per single phase (Note 2)

Peak Current Limit, Cycle-by-

Cycle Accuracy (per phase)

At default ILIM setting

-10

Valley Current Limit (per phase),

Cycle-by-Cycle

ILIM set = 00

ILIM set = 01

ILIM set = 10

ILIM set = 11

Valley Current Limit (per phase),

Cycle-by-Cycle Accuracy

At default ILIM setting

-10

LS FET reverse conduction

current limit (per phase)

Current Limit, Shutdown

% compared to Current Limit, cycle-by-cycle

115

125

135

Current Limit, Warning

% compared to Current Limit, cycle-by-cycle

HS On-Resistance, phase 1

ISW = 1A, VCC5 = 5.0V, Tj < 55OC

Ω

LS On-Resistance, phase 1

ISW = 1A, VCC5 = 5.0V, Tj < 55OC

Ω

HS On-Resistance, phase 2

ISW = 1A, VCC5 = 5.0V, Tj < 55OC

Ω

LS On-Resistance, phase 2

ISW = 1A, VCC5 = 5.0V, Tj < 55OC

Ω

SWx Leakage Current (Note 1)

VIN = 12.0V, VSWx = 0V

µA

VIN = 12.0V, VSWx = 12.0V

µA

Dynamic Voltage Scaling Rate

Configurable in 5mV steps

0.02

mV/us

Configurable in 20mV steps

0.08

mV/us

Output Pull Down Resistance

Pull Down resistance is only connected when

DISPLDN[] = 0 and the regulator is turned off

Ohms

Note 1: The current leakage from SW is not from Power FETs but from active circuitry associated with the SW node of the regulators.

Note 2: Applicable for VIN < 10V. Do not use these settings when VIN > 10V

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