Philips Semiconductors

Product specification

PCK2000

CK97 (66/100MHz) System Clock Generator

1998 Sep 29

5

FUNCTION TABLE

SEL 100/66

CPU/PCI RATIO

CPUCLK (0–3)

(MHz)

CPICLK (1–7)

PCICLK_F

(MHz)

REF (0–2)

IOAPIC (0–1)

(MHz)

48MHz (0–1)

0

2

66.66

33.33

14.318

48

1

3

100

33.33

14.318

48

CLOCK ENABLE CONFIGURATION

CPUSTOP

PCISTOP

PWRDWN

CPUCLK

PCICLK

PCICLK_F

OTHER

CLOCKS

PLLs

OSCILLATOR

X

X

0

LOW

LOW

LOW

Stopped

OFF

OFF

0

0

1

LOW

LOW

33MHz

Running

Running

Running

0

1

1

LOW

33MHz

33MHz

Running

Running

Running

1

0

1

100/66MHz

LOW

33MHz

Running

Running

Running

1

1

1

100/66MHz

33MHz

33MHz

Running

Running

Running

POWER MANAGEMENT REQUIREMENTS

LATENCY

SIGNAL

SIGNAL STATE

NO. OF RISING EDGES OF FREE RUNNING

PCICLK

CPUSTOP

0 (DISABLED)

1

1 (ENABLED)

1

PCISTOP

0 (DISABLED)

1

1 (ENABLED)

1

PWRDWN

1 (NORMAL OPERATION)

3ms

0 (POWER DOWN)

2 MAX

NOTES:

1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the

first valid clock that comes out of the device.

2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.