ATA6621 datasheet(13/27 Pages) ATMEL

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4887D–AUTO–12/06

ATA6621

Figure 3-7.

Power Dissipation: Safe Operating Area versus V

CC Output Current and Supply

Voltage V

S at Different Ambient Temperatures

3.17

Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)

or the PTRIG (positive edge) input within a period time window of T

wd. The trigger signal must

exceed a minimum time t

trigmin > 3 µs. If a triggering signal is not received, a reset signal will be

generated at output NRES. The timing basis of the watchdog is provided by the internal oscilla-

tor, of which the time period T

osc is adjustable via the external resistor Rwd_osc (10 kΩ to 120 kΩ).

In Silent or Sleep Mode, the watchdog is switched off to reduce current consumption.

Minimum time for first watchdog pulse is required after the undervoltage reset at NRES disap-

pears and is defined as lead time t

3.17.1

Typical Timing Sequence with R

wd_osc = 51 kΩ

The trigger signal T

wd is adjustable between 2.9 ms and 33 ms via the external resistor Rwd_osc.

For example, with an external resistor of R

wd_oscSC =51kΩ ±1%, the typical parameters of the

watchdog come out as follows:

OSC = 12.5 µs due to 51 kΩ

d =3922 × 12.5 µs = 49 ms

1 =800 × 12.5 µs = 10 ms

2 =840 × 12.5 µs = 10.5 ms

nres =157 × 12.5 µs = 1.96 ms

VS (V)

amb = 125˚C

amb = 105˚C

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