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PCF8566P bảng dữ liệu(PDF) 27 Page - NXP Semiconductors

tên linh kiện PCF8566P
Giải thích chi tiết về linh kiện  Universal LCD driver for low multiplex rates
PDF  40 Pages
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nhà sản xuất  PHILIPS [NXP Semiconductors]
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PCF8566P bảng dữ liệu(HTML) 27 Page - NXP Semiconductors

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1998 May 04
27
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
11 AC CHARACTERISTICS
VSS =0V; VDD = 2.5 to 6 V; VLCD =VDD − 2.5 to VDD − 6 V; Tamb = −40 to +85 °C; unless otherwise specified; note 1.
Notes
1. All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD.
2. At fCLK < 125 kHz, I2C-bus maximum transmission speed is derated.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fCLK
oscillator frequency (normal mode)
VDD = 5 V; note 2
125
200
315
kHz
fCLKLP
oscillator frequency (power saving
mode)
VDD = 3.5 V
21
31
48
kHz
tCLKH
CLK HIGH time
1
−−µs
tCLKL
CLK LOW time
1
−−µs
tPSYNC
SYNC propagation delay
−−
400
ns
tSYNCL
SYNC LOW time
1
−−µs
tPLCD
driver delays with test loads
VLCD =VDD − 5V
−−
30
µs
I2C-bus
tBUF
bus free time
4.7
−−µs
tHD; STA
START condition hold time
4
−−µs
tLOW
SCL LOW time
4.7
−−µs
tHIGH
SCL HIGH time
4
−−µs
tSU; STA
START condition set-up time
(repeated start code only)
4.7
−−µs
tHD; DAT
data hold time
0
−−µs
tSU; DAT
data set-up time
250
−−
ns
tr
rise time
−−
1
µs
tf
fall time
−−
300
ns
tSU; STO
STOP condition set-up time
4.7
−−µs
Fig.19 Test loads.
handbook, full pagewidth
MGG387
3.3 k
Ω
1.5 k
Ω
6.8 k
Ω
(2%)
(2%)
(2%)
CLK
(pin 4)
SDA, SCL
(pins 1, 2)
SYNC
(pin 3)
0.5VDD
VDD
VDD
S0 to S23
(pins 17 to 40)
Iload ≈ 15 µA
Iload ≈ 25 µA
BP0 to BP3
(pins 13 to 16)



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