PCF8563 datasheet(5/30 Pages) PHILIPS

5 / 30 page

Philips Semiconductors

PCF8563

Real-time clock/calendar

Product speciﬁcation

16 April 1999

5 of 30

9397 750 04855

8.4 Reset

The PCF8563 includes an internal reset circuit which is active whenever the oscillator

is stopped. In the reset state the I2C-bus logic is initialized and all registers, including

the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC

and AE which are set to logic 1.

8.5 Voltage-low detector and clock monitor

The PCF8563 has an on-chip voltage-low detector. When VDD drops below Vlow the

VL bit (Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable

clock/calendar information is no longer guaranteed. The VL ﬂag can only be cleared

by software.

The VL bit is intended to detect the situation when VDD is decreasing slowly for

example under battery operation. Should VDD reach Vlow before power is re-asserted

then the VL bit will be set. This will indicate that the time may be corrupted.

8.6 Register organization

Fig 4.

Voltage-low detection.

handbook, halfpage

VL set

normal power

operation

period of battery

operation

VDD

Vlow

MGR887

Table 4:

Registers overview

Bit positions labelled as ‘

−’are not implemented; those labelled with ‘0’ should always be written with logic 0.

Address Register name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00H

Control/Status 1

TEST1

STOP

TESTC

01H

Control/Status 2

TI/TP

AIE

TIE

0DH

CLKOUT frequency

−−−−−

FD1

FD0

0EH

Timer control

−−−−−

TD1

TD0

0FH

Timer countdown

value

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