PCF8535 datasheet(34/52 Pages) PHILIPS

34 / 52 page

1999 Aug 24

Philips Semiconductors

Objective speciﬁcation

× 133 pixel matrix driver

PCF8535

11 AC CHARACTERISTICS

VDD = 4.5 to 5.5 V; VSS =0V; VLCD = 4.5 to 16.0 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Notes

1. VDD1 to VDD3 =5V.

2. Decoupling capacitor VLCD and VSS = 100 nF (higher capacitor size increases tSU;RESL and higher VDD1 to VDD3

reduces tSU;RESL).

3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

VIL and VIH with an input voltage swing of VSS to VDD.

4. Cb = total capacitance of one bus line in pF.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

ffr(LCD)

LCD frame frequency (internal clock)

165

fclk(ext)

external clock frequency

see Table 20

120

−

410

kHz

tW(RESL)

reset LOW pulse width

−−µs

tW(RESH)

reset HIGH pulse width

−−µs

tSU;RESL

reset LOW pulse set-up time after power-on

notes 1 and 2

−−

µs

tR(op)

end of reset pulse to interface being operational

−−

µs

Serial-bus interface; note 3

fSCL

SCL clock frequency

−

400

kHz

tLOW

SCL clock LOW period

1.3

−−µs

tHIGH

SCL clock HIGH period

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−

0.9

µs

SCL, SDA rise time

note 4

20 + 0.1Cb −

300

SCL, SDA fall time

note 4

20 + 0.1Cb −

300

capacitive load represented by each bus line

−−

400

tSU;STA

set-up time for a repeated START condition

0.6

−−µs

tHD;STA

START condition hold time

0.6

−−µs

tSU;STO

set-up time for STOP condition

0.6

−−µs

tSP

tolerable spike width on bus

−−

tBUF

bus free time between a STOP and START

condition

1.3

−−µs

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