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Fig.1 Block diagram of PCF84C21A; PCF84C41A and PCF84C81A.

MBB561

PORT 0

FLIP-FLOPS

PORT 0

BUFFER

HIGHER

PROGRAM

COUNTER

LOWER

PROGRAM

COUNTER

PROGRAM

STATUS

WORD

MEMORY

BANK

FLIP-FLOPS

RESIDENT ROM

2 kbytes

(PCF84C21A)

4 kbytes

(PCF84C41A)

8 kbytes

(PCF84C81A)

DECODE

58

8

8

8

P0.0 to P0.7

PORT 1

BUFFER

PORT 1

FLIP-FLOPS

P1.0 to P1.7

P2.0 to P2.2

8

8

88

8

8

8

TIMER/

EVENT

COUNTER

32

INTERNAL

CLOCK

FREQ.

30

T1

PORT 2

BUFFER

PORT 2

FLIP-FLOPS

4

8

3

8

SDA/P2.3

INTERFACE

8

SCLK

CLOCK

DATA

OSCILLATOR

RAM

ADDRESS

REGISTER

ACCUMULATOR

TEMPORARY

REGISTER 2

TEMPORARY

REGISTER 1

ARITHMETIC

LOGIC UNIT

INSTRUCTION

REGISTER

&

DECODER

DECIMAL

ADJUST

CONTROL &

TIMING

XTAL 2

XTAL 1

RESET

INT / T0

STOP

IDLE

INTERRUPT

INITIALIZE

CONDITIONAL

BRANCH

LOGIC

INT / T0

T 1

TIMER

FLAG

CARRY

ACC

ACC BIT

TEST

MULTIPLEXER

8 LEVEL STACK

(VARIABLE LENGTH)

OPTIONAL SECOND

REGISTER BANK

DATA STORE

D

E

C

O

D

E

REGISTER 0

REGISTER 1

REGISTER 2

REGISTER 3

REGISTER 4

REGISTER 5

REGISTER 6

REGISTER 7

INTERRUPT

LOGIC

timer interrupt

external interrupt

RESIDENT RAM ARRAY

SIO/

derivative

interrupt

8

Fig.1 Block diagram.