PCF5001T datasheet(34/44 Pages) PHILIPS

34 / 44 page

1997 Mar 04

Philips Semiconductors

Product speciﬁcation

POCSAG Paging Decoder

PCF5001

13 PROGRAMMING CHARACTERISTICS

VDD =0V; VSS =VPG = −5.0 V (see notes 1, 2 and 3); Vref =VSS; pins 2 and 3 open-circuit; Tamb =25 °C.

Quartz crystal parameters: f = 32768 Hz; RS(max) =40kΩ; CL =12pF.

Decoder in OFF status.

Notes

1. VSS =VPG only required during erase/write (tPEW in Fig.19), otherwise VSS(min) = −1.5 V.

2. Maximum voltage for programming (VPG) is −5.5 V.

3. See Section 7.19 and Chapter 8 for limitations of Vref when programming while the voltage converter is enabled.

4. EEPROM programming is also possible at higher frequencies (76.8 kHz or 153.6 kHz). The timings shown then

become proportionally smaller.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Programming; see Fig.19

tRES

power-up reset pulse width

note 4

−−µs

tPEW

erase/write time

−−

fEW

erase/write frequency

1.0

1.5

2.0

MHz

tEW

erase/write cycles

1000

10000

−−

tDR

data retention time

Tamb =85 °C10

−−

years

tPCH

data clock HIGH time

note 4

−−µs

tPCL

data clock LOW time

note 4

−−µs

tPRS

read set-up time

note 4

−−

µs

tPSI

data set-up time on input

note 4

−−µs

tPSO

data set-up time on output

note 4

−−

µs

tPDH

data hold time

note 4

−−µs

handbook, halfpage

MGL100

tDI1

tDI0

t TDI

Fig.21 Data input timing.

PCF5001T bảng dữ liệu(PDF) 34 Page - NXP Semiconductors

PCF5001T bảng dữ liệu(HTML) 34 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

bảng dữ liệu tải về

Link URL