PQFP100 datasheet(423/429 Pages) STMICROELECTRONICS

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ST92F124/F150/F250 - KNOWN LIMITATIONS

KNOWN LIMITATIONS (Cont’d)

13.8 EMULATION CHIP LIMITATIONS

Additional limitations exist on Emulation chips (EMU2 emulator). These limitations correspond to those

present in AxxxxxxxxY trace codes (ST92F150). They are listed in the following table.

13.8.1

RESET

BEHAVIOUR

FOR

BI-

DIRECTIONAL, WEAK PULL-UP PORTS

This section applies to ports P1[7:3], P4[1], P8[7:2]

and P9[7:0].

During the reset phase (external reset signal low)

and the delay of 20400 clock periods (tRSPH) fol-

lowing a reset, these ports are in High Impedance

state, while according to the datasheet they should

have weak pull-ups. These ports then enter Weak

Pull-up state until the user overwrites the reset

values of I/O Port Control Registers PxC0, PxC1

and PxC2.

Table 76. Reset Behaviour Table

Shaded areas represent erroneous operations.

Section

Limitation (AxxxxxxxxY trace code)

Section 13.8.1

RESET BEHAVIOUR FOR BI-DIRECTIONAL, WEAK PULL-UP PORTS

Section 13.8.2

HIGH DRIVE I/Os WHEN BSZ=1

Section 13.8.3

ADC PARASITIC DIODE

Section 13.8.4

ADC ACCURACY VS. NEGATIVE INJECTION CURRENT

Section 13.8.5

I2CECCR REGISTER LIMITATION

Section 13.8.6

I2C BEHAVIOUR DISTURBED DURING DMA TRANSACTIONS

Section 13.8.7

MFT DMA MASK BIT RESET

Section 13.8.8

DMA DATA CORRUPTED BY MFT INPUT CAPTURE

Section 13.8.9

SCI-A WRONG BREAK DURATION

Section 13.8.10

LIN MASTER MODE NOT PRESENT ON SCI-A

Section 13.8.11

LIMITATIONS ON LQFP64 PACKAGES

Port

Datasheet

Condition

Rev Z Behaviour

Port Behaviour

Control Register Value

While RESET

is low

During next

20K Clock

Cycles

After these

20K Clock

Cycles

PxC0

PxC1

PxC2

P1[7:3]

Bi-Dir + WPU

Hi-Z

Bi-Dir + WPU

P4.1

Bi-Dir + WPU

Hi-Z

Bi-Dir + WPU

P8[7:2]

Bi-Dir + WPU

Hi-Z

Bi-Dir + WPU

P9[7:0]

Bi-Dir + WPU

Hi-Z

Bi-Dir + WPU

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