PCF2105MUSLASH2 datasheet(29/48 Pages) PHILIPS

29 / 48 page

1998 Jul 30

Philips Semiconductors

Product speciﬁcation

LCD controller/driver

PCF2105

Notes

1. VDD = 5.0 V.

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

VIL and VIH with an input voltage swing of VSS to VDD.

3. CL = total capacitance of one bus line in pF and R = 100 Ω.

4. A fast mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

tr(max) +tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line

is released.

5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL

signal) in order to bridge the undefined region of the falling edge of SCL.

6. The maximum tHD;DAT has only to be met if the device does not stretch tLOW of the SCL signal.

Timing characteristics: I2C-bus interface; note 2; see Fig.25

fSCL

SCL clock frequency

−−

400

kHz

tSW

tolerable spike width on bus

−−

tBUF

bus free time

1.3

−−

µs

tSU;STA

set-up time for a repeated START

condition

0.6

−−

µs

tHD;STA

START condition hold time

0.6

−−

µs

tLOW

SCL LOW time

1.3

−−

µs

tHIGH

SCL HIGH time

0.6

−−

µs

SCL and SDA rise time

note 3

−

20 + RCL

300

SCL and SDA fall time

note 3

−

20 + RCL

300

tSU;DAT

data set-up time

note 4

100

−−

tHD;DAT

data hold time

notes 5 and 6

−

0.9

µs

tSU;STO

set-up time for STOP condition

0.6

−−

µs

load capacitance for each bus line

−−

400

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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