PSD835G2V_07 datasheet(49/118 Pages) STMICROELECTRONICS

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PSD835G2V

Memory ID registers

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Memory ID registers

The 8-bit Read-Only Memory Status Registers are included in the CSIOP space. The user

can determine the memory configuration of the PSD device by reading the Memory ID0 and

ID1 Registers. The contents of the registers are defined in Table 25 and Table 26. on page

28.

PLDs

The PLDs bring programmable logic functionality to the PSD. After specifying the logic for

the PLDs in PSDsoft, the logic is programmed into the device and available upon Power-up.

The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The

PLDs are briefly discussed in the next few paragraphs, and in more detail in Decode PLD

(DPLD) on page 52, and in Complex PLD (CPLD) on page 53. Figure 12. on page 51 shows

the configuration of the PLDs.

The DPLD performs address decoding for Select signals for internal components, such as

memory, registers, and I/O ports.

The CPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, and encoding and decoding logic. These logic functions can be constructed

using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The

CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.

The AND Array is used to form product terms. These product terms are specified using

PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are

shown in Table 30.

15.1

The Turbo Bit in PSD

The PLDs in the PSD can minimize power consumption by switching to standby when inputs

remain unchanged for an extended time of about 70ns. Resetting the Turbo bit to 0 (Bit 3 of

PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the

Turbo mode off increases propagation delays while reducing power consumption. See

Power management on page 84, on how to set the Turbo bit.

Additionally, five bits are available in PMMR2 to block MCU control signals from entering the

PLDs. This reduces power consumption and can be used only when these MCU control

signals are not used in PLD logic equations.

Each of the two PLDs has unique characteristics suited for its applications. They are

described in the following sections.

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