VT6306L datasheet(49/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

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Functional Descriptions

Remote Access and Reply Packets

The VT6306 PHY supports remote access (see Figure 10) to its internal registers. On receipt of a remote access packet addressed

to the node (either from the bus or from the host), the VT6306 PHY will immediately respond with the appropriate remote reply

packet (seeFigure 11). The remote access packet and the reply packet are also forwarded to the local link. The fields in the remote

access and remote reply packets are interpreted as shown in the table below.

Note: Bit 0 (the lsb) is on the left in the above diagram

Figure 10. Remote Access Packet Format

Note: Bit 0 (the lsb) is on the left in the above diagram

Figure 11. Remote Reply Packet Format

Table 10. Remote Access and Remote Reply Packet Fields

Field Name

Meaning

Phy_ID

Physical node identifier of the destination of the packet (type = 1 or 5)

Physical node identifier of the source of the packet (type = 3 or 7)

Type

Type 1 - register read of the base registers

Type 3 - register contents (base registers)

Type 5 - register read of the paged registers

Type 7 - register contents (paged registers)

Page

Page 0 - Port Status Page

Page 1 - Product Identification Page

Page 2 - 6 - these pages are not implemented, the chip always responds with zero

Page 7 contents is reserved for testing

Port

Port. Identify the port for the selected register page. For values 0, 1, 2 and 3, the page is as

defined in Table 5 (PHY Register Page 0 Bit Field Descriptions). For all other values the

VT6306 always responds with zero.

Reg

If type = 1, then reg directly addresses one of the base registers.

If type = 5, then reg addresses 1000b +reg in the selected page and port.

Data

Current value of the VT6306 register addressed by the immediately preceding Remote

Access packet (reserved and unimplemented fields and registers are returned as zero).

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