COM

Y

Y2

A

INH

Y1

COM

5

2

7

6

1

SW

SW

15

SN74LVC2G53

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SCES324Q – JULY 2001 – REVISED JANUARY 2019

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8 Detailed Description

8.1 Overview

This dual analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G53 device can handle both analog and digital signals. This device permits signals with

amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

8.2 Functional Block Diagram

NOTE: For simplicity, the test conditions shown in Figure 1 through Figure 4 and Figure 6 through Figure 10 are for the

demultiplexer configuration. Signals can be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.

Figure 11. Logic Diagram

Figure 12. Logic Diagram, Each Switch (SW)

8.3 Feature Description

A high-level voltage applied to INH disables the switches. When INH is low, signals can pass from A to Y or Y to

A. Low ON-resistance of 6.5 Ω at 4.5-V VCC is ideal for analog signal conditioning systems. The control signals

can accept voltages up to 5.5 V without VCC connected in the system. Combination of lower tpd of 0.8 ns at 3.3 V

and low enable and disable time make this part suitable for high-speed signal switching applications.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74LVC2G53.

Table 1. Function Table

CONTROL

INPUTS

ON

CHANNEL

INH

A

L

L

Y1

L

H

Y2

H

X

None