5.2 Pin Attributes and Signal Descriptions

This section describes the AM625SIP device pins which have different power or signal functions relative to the

ALW packaged AM6254 device. The AM6254 DDRSS0 signals in the ALW package that would normally connect

to an external SDRAM were connected directly to an integrated LPDDR4 SDRAM in the AM625SIP device, and

the pins associated with these signals were reassigned to different power or signal functions. Table 5-1 contains

a list of ball numbers that were reassigned to new power or signal functions along with their new ball name and

signal description.

Table 5-1. Reassigned DDRSS0 Pins on the AMK Package

BALL

NUMBER

BALL NAME

Signal Description

M9

VDDS_DDR

DDR PHY IO supply

F2

VDDS_MEM_1P1

SDRAM IO supply

(Sources the SDRAM VDD2 and VDDQ power rails)

G2

H1

H2

N1

N2

P2

R2

U1

U2

V2

W2

M4

VDDS_MEM_1P8

SDRAM Core supply

(Sources the SDRAM VDD1 power rail)

N3

R3

DDR_ZQ

SDRAM Calibration Reference(1)

(Connects to the SDRAM ZQ Calibration Reference)

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AM625SIP

SPRSP98 – NOVEMBER 2023

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