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AM2732 bảng dữ liệu(PDF) 74 Page - Texas Instruments

tên linh kiện AM2732
Giải thích chi tiết về linh kiện  AM273x Sitara™ Microcontrollers
PDF  114 Pages
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Trang chủ  http://www.ti.com
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AM2732 bảng dữ liệu(HTML) 74 Page - Texas Instruments

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1
mii _txclk
n
(input)
miin_txd3
miin_txen, miin_txer
−
,
(outputs)
miin_txd0
Figure 6-15. GMAC Transmit Interface Timing MIIn operation
6.12.3.3.11 MII Receive Clock Timing Requirements
NO.
PARAMETER
DESCRIPTION
SPEED
MIN
MAX
UNIT
1
tc(RX_CLK)
Cycle time, miin_rxclk
10 Mbps
400
ns
100 Mbps
40
ns
2
tw(RX_CLKH)
Pulse duration, miin_rxclk high
10 Mbps
140
260
ns
100 Mbps
14
26
ns
3
tw(RX_CLKL)
Pulse duration, miin_rxclk low
10 Mbps
140
260
ns
100 Mbps
14
26
ns
4
tt(RX_CLK)
Transition time, miin_rxclk
10 Mbps
3
ns
100 Mbps
3
ns
mii _rxclk
n
2
3
1
4
4
Figure 6-16. Clock Timing (GMAC Receive) - MIIn operation
6.12.3.3.12 MII Receive Timing Requirements
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
tsu(RXD-RX_CLK)
Setup time, receive selected signals valid before miin_rxclk
8
ns
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
2
th(RX_CLK-RXD)
Hold time, receive selected signals valid after miin_rxclk
8
ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
mii _rxclk
n
(Input)
1
2
mii _rxd3
n
mii _rxdv miin_rxer
−
,
(Inputs)
mii _rxd0,
n
n
Figure 6-17. GMAC Receive Interface Timing MIIn operation
AM2732, AM2732-Q1
SWRS245B – DECEMBER 2021 – REVISED DECEMBER 2023
www.ti.com
74
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Product Folder Links: AM2732 AM2732-Q1



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