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Yx,FBOUT

YxFBOUT

,

T0178-01

f

n= AnyHalfCycle

f

0

1

t

(hper_n)

t

(hper_n+1)

t

2 f

1

ClockInputs

andOutputs

80%

20%

80%

20%

t

r

t

f

V

,V

OH

IH

V ,V

OL

IL

t

t

r

V

– V

80%

20%

t

t

f

V

– V

80%

20%

T0179-01

V

DDQ

AV

DD

AGND

GND

Card

Via

Card

Via

4.7 F

1206

m

0.1 F

0603

m

2200pF

0603

(1)

PLL

S0232-01

Bead

0603

(2)

CDCVF855

SCAS839A – APRIL 2007 – REVISED MAY 2007

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 8. Half-Period Jitter

Figure 9. Input and Output Slew Rates

(1)

Place the 2200-pF capacitor close to the PLL.

(2)

Recommended bead: Fair-Rite P/N 2506036017Y0 or equilvalent (0.8

Ω dc maximum, 600 Ω at 100 MHz).

NOTE: Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect

trace to one GND via (farthest from the PLL).

9

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