www.ti.com

FEATURES

APPLICATIONS

SDA/SCL

Differential

LVDSInput

Upto650MHz

5Differential

CMLOutputs

Upto650MHz

5Differential

CMLOutputs

Upto650MHz

DIVIDER

DIVIDER

CDCL1810

SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007

1.8V, 10 Output, High-Performance Clock Distributor

• Output Enable Control for Each Output

• Single 1.8V Supply

• SDA/SCL Device Management Interface

• High-Performance Clock Distributor with 10

• 48-pin QFN (RGZ) Package

Outputs

• Industrial Temperature Range: –40°C to +85°C

• Low Input-to-Output Additive Jitter:

As Low As 10fs RMS

• Clock Synthesis and Distribution for

• Output Group Phase Adjustment

High-Speed SERDES

• Low-Voltage Differential Signaling (LVDS)

• Synthesis and Distribution of SERDES

Input, 100

Ω Differential On-Chip Termination,

Reference Clocks for 1G/10G Ethernet,

Up to 650MHz Frequency

1X/2X/4X/10X Fibre Channel, PCI Express,

• Differential Current Mode Logic (CML)

Serial ATA, SONET, CPRI, OBSAI, etc.

Outputs, 50

Ω Single-Ended On-Chip

• Up to 1-to-10 Clock Buffering and Fan-out

Termination, Up to 650MHz Frequency

• Two Groups of Five Outputs Each with

Independent Frequency Division Ratios

• Output Frequency Derived with Divide Ratios

of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80

• Meets ANSI TIA/EIA-644-A-2001 LVDS

Standard Requirements

• Power Consumption: 410mW Typical

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.